1. Field of the Invention
This invention relates to personal computer systems having high-speed memory. More particularly, it relates to such systems having the facility for expanding the high-speed memory with minimum impact on the capacity for input/output connections.
2. Description of the Prior Art
When Industry Standard Architecture (ISA) personal computers were introduced, high-speed memory capacity of 64 K bytes up to 256 K bytes was located on the main circuit board. These computers also contained an input/output (I/O) expansion capability which generally provided eight (8) slots for connection with the I/O channel which was incorporated in the main logic board. The memory was then expanded, as desired, through the use of plug-in adapter cards, plugged into the I/O channel. Memory on the I/O channel and memory on the memory channel had equivalent performance.
As higher speed processors and wider data paths (i.e., 32-bit versus 16-bit), as well as requirements for more and more high-speed memory led to architectures that could run the memory channel much faster than the I/O channel. Because of the performance impact (overall performance is tightly coupled to memory performance), it was desirable to allow maximum memory expansion on the dedicated memory channel. However, because of the form factor of existing personal computer chassis, the problem of providing large memory capacities on the dedicated memory channel was difficult.
A prior art scheme for providing a large amount of high-speed memory was to use a dedicated full-length memory card connected to the memory channel. A disadvantage with this solution is that the memory card extended over one of the eight available I/O expansion slots, making that slot useless.
Another prior art approach has been to provide Single In-line Memory Modules (SIMMs) in the allocated space for high-speed memory on the main logic board. This technique permitted a total memory capacity of 8 Megabytes. Any expansion of memory above 8 Megabytes had to be performed on the I/O channel which resulted in slow memory for the upper addresses as well as resulting in at least one full-length expansion slot being occupied.